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arxiv: 2607.00769 · v1 · pith:LD5IPU2Rnew · submitted 2026-07-01 · ❄️ cond-mat.mes-hall · cond-mat.supr-con

Universal logic circuit for gate-controlled superconductor-based switches operating at liquid-helium temperatures

Martin Berke , L\H{o}rinc Kup\'as , Tosson Elalaily , M\'at\'e S\"ut\H{o} , Szabolcs Csonka , P\'eter Makk This is my paper

Pith reviewed 2026-07-02 07:08 UTC · model grok-4.3

classification ❄️ cond-mat.mes-hall cond-mat.supr-con
keywords gate-controlled supercurrentsuperconducting nanowireslogic gatessuperconducting electronicshalf-adderside-gate electrodesliquid helium temperatures
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The pith

Gate-controlled superconducting nanowires realize all classical logic gates and the half-adder using at most three devices.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper establishes that the gate-controlled supercurrent effect in superconducting nanostructures can be harnessed to build a functionally complete set of logic gates. By configuring individual nanowires with two side-gate electrodes, the authors show explicit realizations of AND, OR, NOT, and COPY operations. These primitives suffice for any Boolean function, including the half-adder circuit, all within a maximum of three nanowires. The layout is presented as scalable and compatible with fast switching observed in related experiments, positioning the device as a candidate building block for classical hybrid supercomputers at liquid-helium temperatures.

Core claim

A universal logic circuit based on gate-controlled supercurrent switches in superconducting nanowires demonstrates AND, OR, NOT and COPY gates; the same approach enables every classical logic gate and the half-adder combinational circuit when at most three nanowires, each fitted with two side-gate electrodes, are used.

What carries the argument

The gate-controlled supercurrent effect realized in individual superconducting nanowires each equipped with two side-gate electrodes, allowing voltage-tuned switching between zero-resistance and finite-resistance states.

If this is right

  • Any Boolean function can be constructed from the demonstrated AND, OR, NOT and COPY primitives.
  • The half-adder requires no more than three nanowires.
  • The general device layout supports scaling to larger combinational circuits.
  • Fast switching and small voltage signals reported in related work make the circuit a functional element in superconducting electronics.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Cryogenic hybrid computers could incorporate these switches alongside conventional superconducting elements without requiring entirely new fabrication flows.
  • If gate voltages can be shared or multiplexed, power and wiring overhead at millikelvin temperatures might be reduced compared with resistive logic.
  • The same nanowire geometry might be tested for compatibility with existing superconducting qubit control lines.

Load-bearing premise

The gate-controlled supercurrent effect remains stable and independently controllable when multiple nanowires are wired together into one circuit.

What would settle it

Demonstration of crosstalk, loss of gate control, or inability to produce the half-adder output when two or three nanowires are integrated on the same chip.

Figures

Figures reproduced from arXiv: 2607.00769 by L\H{o}rinc Kup\'as, Martin Berke, M\'at\'e S\"ut\H{o}, P\'eter Makk, Szabolcs Csonka, Tosson Elalaily.

Figure 1
Figure 1. Figure 1: Device configuration (a) The device consists of three NWs (blue) that are connected to a common line (green) at one end, and there are two more contacts (green) at the other end of each NW. Each NW is con￾trolled by two side gate electrodes (orange). (b) Optical microscope image of a device. Scale bar: 25 µm (c) SEM image of the active region of the device showing the wire and the gate electrodes Scale bar… view at source ↗
Figure 2
Figure 2. Figure 2: Suppression of the supercurrent with gating the device and logic operation principle (a) V − I curve of a NW measured at 4 K. (b) The critical cur￾rent of a NW as a function of the applied gate voltage on one of the side-gate electrodes (red) and the leakage current calculated from the voltage drop measured across a pre-resistor (blue). With increasing gate voltage on the side-gate electrode, the critical … view at source ↗
Figure 3
Figure 3. Figure 3: Logic gates operation for the AND, OR, NOT and COPY gates. (a)-(d) The schematic circuit diagram for the AND, OR, NOT and COPY gates. The input signals inputA and inputB represent the additional gate voltage on top of the gate voltage setting the working point on panels (e)-(h). (e) The logic operation of the AND gate. There is a clear increase in the output voltage (green) as the function of time, when bo… view at source ↗
read the original abstract

The observation of the gate-controlled supercurrent (GCS) effect in superconducting nanostructures initiated major research efforts toward the realisation of superconducting-based computing architectures. Here we introduce a universal logic circuit that can be a promising superconducting building block of classical hybrid supercomputers. We demonstrate a functionally complete set of logic gates by realising the AND, OR, NOT and COPY gates. The general layout and scalability of our device, combined with recent experiments demonstrating fast switching and small voltage signals, make it a functional candidate in superconducting electronics. Our device enables the realization of all classical logic gates and the half-adder combinational logic circuit using at most three nanowires, each uniquely configured with two side-gate electrodes.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

1 major / 1 minor

Summary. The manuscript introduces a universal logic circuit based on the gate-controlled supercurrent (GCS) effect in superconducting nanowires. It reports experimental demonstration of AND, OR, NOT, and COPY gates and asserts that this layout enables realization of all classical logic gates plus a half-adder combinational circuit using at most three nanowires, each configured with two side-gate electrodes. The work targets hybrid superconducting electronics operating at liquid-helium temperatures, citing potential advantages in speed and voltage signals.

Significance. If the multi-nanowire integration claims hold, the approach could supply a compact, functionally complete building block for superconducting logic that reduces the number of elements needed per gate. The emphasis on side-gate control and few-nanowire topologies is a concrete design choice that, if experimentally validated at circuit level, would strengthen the case for GCS-based classical computing.

major comments (1)
  1. [Abstract] Abstract: the central claim that the device 'enables the realization of all classical logic gates and the half-adder combinational logic circuit using at most three nanowires' rests on an untested assumption of independent, crosstalk-free operation when multiple GCS nanowires are combined. No truth table, schematic, or simultaneous measurement data for the half-adder (or any three-nanowire circuit) is referenced, so the universality assertion beyond the four demonstrated single-gate cases remains unsupported.
minor comments (1)
  1. [Abstract] The abstract refers to 'recent experiments demonstrating fast switching and small voltage signals' without citations; adding the relevant references would clarify the performance context.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for their detailed review and address the major comment on the abstract claim below. The response clarifies the basis for the universality statement while acknowledging the distinction between demonstrated single-nanowire gates and proposed multi-nanowire circuits.

read point-by-point responses

  1. Referee: [Abstract] Abstract: the central claim that the device 'enables the realization of all classical logic gates and the half-adder combinational logic circuit using at most three nanowires' rests on an untested assumption of independent, crosstalk-free operation when multiple GCS nanowires are combined. No truth table, schematic, or simultaneous measurement data for the half-adder (or any three-nanowire circuit) is referenced, so the universality assertion beyond the four demonstrated single-gate cases remains unsupported.

    Authors: The experimental results in the manuscript are limited to single-nanowire realizations of AND, OR, NOT, and COPY, each using one nanowire with two side gates. The claim that the same device layout enables all classical gates and a half-adder with at most three nanowires is a design statement: the manuscript provides explicit schematics, gate configurations, and truth tables showing how different logic functions are obtained by wiring the three nanowires and applying appropriate gate voltages to each. These configurations rely on the independently addressable side gates demonstrated in the single-nanowire experiments. The assumption of negligible crosstalk follows from the physical separation and individual gate control used in the fabricated devices; no simultaneous multi-nanowire data are presented because the work focuses on establishing the basic gate primitives and the resulting circuit topology. We can add a sentence in the abstract and discussion to distinguish demonstrated gates from the proposed multi-nanowire realizations. revision: partial

Circularity Check

0 steps flagged

No circularity: experimental demonstration with no derivation chain

full rationale

The paper is an experimental report on fabricated nanowire devices demonstrating AND/OR/NOT/COPY gates via gate-controlled supercurrent. No equations, fitted parameters, or mathematical derivations are present in the abstract or described claims. The universality statement is an engineering assertion about device layout scalability rather than a self-referential prediction or self-citation load-bearing step. No patterns from the enumerated circularity kinds apply.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

Experimental demonstration paper; the central claim rests on the existence and controllability of the gate-controlled supercurrent effect in the described nanowire geometry.

axioms (1)
  • domain assumption The gate-controlled supercurrent effect can be used to implement stable AND, OR, NOT and COPY operations in integrated nanowire circuits.
    Invoked by the claim that the demonstrated gates form a functionally complete set.

pith-pipeline@v0.9.1-grok · 5681 in / 1146 out tokens · 25752 ms · 2026-07-02T07:08:17.420298+00:00 · methodology

discussion (0)

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