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Heterogeneous GPU-FPGA systems accelerate LLM memory processing up to 2.2x by offloading sparse operations.

2026-05-14 00:22 UTC pith:PBIHCRXC

load-bearing objection The paper frames LLM memory work as a four-step pipeline and shows GPU-FPGA offload can cut end-to-end time and energy, but the gains hinge on whether data movement costs stay low. the 2 major comments →

arxiv 2603.29002 v3 pith:PBIHCRXC submitted 2026-03-30 cs.DC cs.AI

Understand and Accelerate Memory Processing Pipeline for Large Language Model Inference

Zifan He , Rui Ma , Yizhou Sun , Jason Cong This is my paper
classification cs.DC cs.AI
keywords LLM inferencememory processing pipelineheterogeneous systemsFPGA offloadingsparse attentionretrieval augmented generationenergy efficiencydisaggregated inference
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper shows that sparse attention, retrieval-augmented generation, and related LLM optimizations unify into one four-step memory processing pipeline of Prepare Memory, Compute Relevancy, Retrieval, and Apply to Inference. Systematic profiling reveals this pipeline consumes 22 to 97 percent of total inference time and exhibits strong heterogeneity between dense and irregular memory-bound work. The authors demonstrate that mapping the irregular portions to an FPGA while leaving compute-heavy steps on a GPU produces concrete speed and energy gains over a pure GPU baseline. This establishes heterogeneous hardware as a practical route to lower overhead in long-context LLM inference.

Core claim

The authors unify several LLM optimizations into a four-step memory processing pipeline and show that a GPU-FPGA heterogeneous system, by offloading sparse irregular and memory-bounded operations to the FPGA, delivers up to 2.2 times faster execution and up to 4.7 times lower energy use than a GPU-only baseline across multiple models and inputs.

What carries the argument

The four-step memory processing pipeline that consolidates Prepare Memory, Compute Relevancy, Retrieval, and Apply to Inference steps, exposing workload heterogeneity that maps naturally to GPU-FPGA division.

Load-bearing premise

The assumption that data-transfer costs between GPU and FPGA stay small enough not to cancel the offloading gains and that the observed heterogeneity pattern holds for other LLMs and inputs.

What would settle it

A direct measurement on a standard long-context LLM showing GPU-FPGA transfer latency exceeding the computation savings, producing zero or negative net speedup.

Watch this falsifier — get emailed when new claim-graph text bears on it.

If this is right

  • End-to-end LLM inference latency drops when memory-bounded steps move to FPGAs.
  • Energy per token falls substantially for workloads dominated by sparse attention or RAG.
  • Heterogeneous systems become a concrete architecture choice for disaggregated LLM serving.
  • Hardware designers gain guidance on interconnect requirements for memory pipelines.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same offloading logic could extend to other accelerator pairings such as GPU-ASIC or multi-FPGA setups.
  • Dynamic profiling at runtime might further improve the mapping decisions for varying context lengths.
  • The pipeline abstraction could help compare future memory-centric accelerators without re-profiling entire models.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

2 major / 1 minor

Summary. The manuscript unifies sparse attention, RAG, and compressed-memory optimizations into a four-step memory processing pipeline (Prepare Memory, Compute Relevancy, Retrieval, Apply to Inference). Profiling on GPU reveals 22–97 % memory-processing overhead with heterogeneous compute characteristics; the authors therefore offload sparse/irregular/memory-bound steps to an Alveo U55C FPGA while retaining dense compute on an AMD MI210 GPU (and similarly on A100), reporting up to 2.2× end-to-end speedup and 4.7× energy reduction versus a pure-GPU baseline.

Significance. If the measured speedups and energy gains are reproducible, the work supplies concrete evidence that heterogeneous GPU-FPGA platforms can profitably target the memory-bound fraction of modern LLM inference. The explicit pipeline abstraction and real-hardware numbers on two GPU platforms constitute a practical contribution that can inform both system software and future heterogeneous accelerator design.

major comments (2)
  1. [Evaluation] Evaluation section (and abstract): the 2.2× speedup and 4.7× energy claims rest on offloading Prepare Memory / Compute Relevancy / Retrieval to the FPGA, yet no breakdown of PCIe (or equivalent) transfer latency versus kernel execution time is provided for the moved data structures (KV caches, attention scores, embeddings). Without this accounting, it is impossible to determine whether interconnect costs erode the reported net gains, especially at longer contexts or larger batches.
  2. [§3 and Evaluation] §3 (profiling) and Evaluation: the paper states concrete overhead percentages and speedup numbers but supplies no description of the exact baseline implementation, measurement methodology (wall-clock vs. kernel time, power sampling interval, error bars), workload selection (models, context lengths, batch sizes), or how the FPGA kernels were integrated with the GPU runtime. These omissions make the central empirical claim unverifiable from the text.
minor comments (1)
  1. [Abstract] Abstract, first sentence: 'increasingly depends' should read 'increasingly depend'.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive comments, which highlight opportunities to strengthen the verifiability of our empirical results. We will revise the manuscript to incorporate the requested details.

read point-by-point responses

  1. Referee: [Evaluation] Evaluation section (and abstract): the 2.2× speedup and 4.7× energy claims rest on offloading Prepare Memory / Compute Relevancy / Retrieval to the FPGA, yet no breakdown of PCIe (or equivalent) transfer latency versus kernel execution time is provided for the moved data structures (KV caches, attention scores, embeddings). Without this accounting, it is impossible to determine whether interconnect costs erode the reported net gains, especially at longer contexts or larger batches.

    Authors: We agree that a breakdown of PCIe transfer latency versus kernel execution time is necessary to fully substantiate the net gains. In the revised manuscript we will add profiling tables and figures in the Evaluation section that separately report PCIe transfer times and FPGA kernel execution times for KV caches, attention scores, and embeddings, measured across the evaluated context lengths and batch sizes. These additions will allow direct assessment of whether interconnect overheads reduce the reported speedups and energy benefits. revision: yes

  2. Referee: [§3 and Evaluation] §3 (profiling) and Evaluation: the paper states concrete overhead percentages and speedup numbers but supplies no description of the exact baseline implementation, measurement methodology (wall-clock vs. kernel time, power sampling interval, error bars), workload selection (models, context lengths, batch sizes), or how the FPGA kernels were integrated with the GPU runtime. These omissions make the central empirical claim unverifiable from the text.

    Authors: We acknowledge that the current text lacks sufficient methodological detail for reproducibility. The revised version will expand §3 and the Evaluation section with: (1) the precise baseline implementation (PyTorch 2.1 with FlashAttention-2 and specific compilation flags); (2) measurement methodology (wall-clock time captured via CUDA events on GPU and equivalent FPGA timers, power sampled via nvidia-smi at 100 ms intervals with error bars from 5 runs); (3) complete workload parameters (LLaMA-7B/13B models, context lengths 2K–32K tokens, batch sizes 1–16); and (4) integration specifics (PCIe data-transfer protocol and runtime API calls used to invoke FPGA kernels from the GPU host process). revision: yes

Circularity Check

0 steps flagged

No circularity; claims rest on direct empirical measurements

full rationale

The paper contains no equations, fitted parameters, or derivation chain that could reduce to its own inputs. The four-step memory pipeline is presented as a conceptual unification of existing LLM optimizations (sparse attention, RAG, etc.) identified via profiling; it is not defined in terms of the claimed speedups. The central results—up to 2.2× speedup and 4.7× energy reduction—are reported as direct hardware measurements on the AMD MI210 + Alveo U55C platform versus a GPU baseline. No self-citation is invoked to justify uniqueness or to force a result, and no ansatz or renaming of a known pattern is used to generate the performance numbers. The work is therefore self-contained against external benchmarks and receives a score of 0.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The claim depends on the representativeness of the profiled workloads and the assumption that FPGAs can absorb the irregular memory operations with low integration cost; no free parameters or new entities are introduced.

axioms (1)
  • domain assumption The computational heterogeneity observed in the profiled LLM workloads is representative of real-world inference scenarios.
    The paper uses this to justify FPGA offloading; it is stated via the profiling results but not proven for all models.

pith-pipeline@v0.9.0 · 5519 in / 1356 out tokens · 68016 ms · 2026-05-14T00:22:39.912975+00:00 · methodology

0 comments
read the original abstract

Modern large language models (LLMs) increasingly depends on efficient long-context processing and generation mechanisms, including sparse attention, retrieval-augmented generation (RAG), and compressed contextual memory, to support complex reasoning. We show that these optimizations can be unified into a four-step memory processing pipeline: Prepare Memory, Compute Relevancy, Retrieval, and Apply to Inference. Through systematic profiling, we identify a 22%-97% memory processing overhead in LLM inference and strong heterogeneity in its computational characteristics. Motivated by this insight, we argue that \textbf{heterogeneous systems} are well-suited to accelerate memory processing and thus end-to-end inference. We demonstrate this approach on a GPU-FPGA system by offloading sparse, irregular, and memory-bounded operations to FPGAs while retaining compute-intensive operations on GPUs. Evaluated on an AMD MI210 GPU and an Alveo U55C FPGA, our system is up to $2.2\times$ faster and achieves up to $4.7\times$ less energy across multiple LLM inference optimizations than the GPU baseline (similar results hold on NVIDIA A100). These results establish heterogeneous systems as a practical direction for efficient LLM memory processing and inform future heterogeneous hardware design.

Figures

Figures reproduced from arXiv: 2603.29002 by Jason Cong, Rui Ma, Yizhou Sun, Zifan He.

Figure 1
Figure 1. Figure 1: The GPU-FPGA heterogeneous system (1 MI210 + 1 Alveo U55C) can provide 1.2 − 1.8× speedup and 1.3 − 4.7× en￾ergy cost reduction consistently over a wide range of long-context LLM inference optimizations. “SA-R” stands for SeerAttention-R and “DSA” stands for DeepSeek Attention. ability to memorize and process long inputs. State-of-the-art models (Comanici et al., 2025; Shen et al., 2025; Grattafiori et al.… view at source ↗
Figure 2
Figure 2. Figure 2: Four-Step Memory Processing Pipeline in LLMs: Prepare Memory preprocesses and structures raw memory for efficient access; Compute Relevancy assigns relevance scores to memory entries with respect to the input query; Retrieval extracts the most relevant memory based on these scores; and Apply to Inference integrates retrieved content and input into intermediate outputs, used in the rest operations in LLMs t… view at source ↗
Figure 4
Figure 4. Figure 4: Percentage of latency on memory processing for RAG using the Wikipedia dump (Su et al., 2024). For two-stage RAG, reranking is time consuming, leading to a high percentage at 500K and slow increment as document count grows [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗
Figure 3
Figure 3. Figure 3: Percentage of latency spent on memory processing for sparse attention methods. With 1M tokens, memory processing can take 22%–81% of the decoding time. By profiling the latency breakdowns of LLM inference op￾timizations based on the experimental settings illustrated in Section 6.1, we observe a large proportion of inference latency is spent on memory processing as the memory size increases. For sparse atte… view at source ↗
Figure 6
Figure 6. Figure 6: Kernel mapping and data communication on the GPU-FPGA system. (a) Sparse attention and RAG employ general setup, where the GPU prepares the memory and apply to tthe inference and the FPGA execute an efficient fused kernel for compute relevancy and retrieval. (b) For MemAgent, we utilize prefill-decode disaggregation where the FPGA operates LLM decoding and the GPU handles prefilling. (c) For Memory as Cont… view at source ↗
Figure 7
Figure 7. Figure 7: illustrates the FPGA kernel architecture. Here, we use DeepSeek Attention as an example for illustrating the computations. One advantage of FPGAs over GPUs is that [PITH_FULL_IMAGE:figures/full_fig_p006_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: End-to-end speedup of the GPU-FPGA heterogeneous system over the baseline for sparse attention mechanisms [PITH_FULL_IMAGE:figures/full_fig_p007_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Speedup for the memory processing steps deployed on the GPU-FPGA heterogeneous system for sparse attentions. Each method benefits from the GPU-FPGA system in three aspects: 1) the FPGA’s large, high-bandwidth on￾chip memory permits faster data access than the GPU; 2) operations within or across memory processing steps are 7 [PITH_FULL_IMAGE:figures/full_fig_p007_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Left: End-to-end speedup of the GPU-FPGA system over the baseline for RAG. Right: Speedup of memory processing for the single stage RAG (DRAGIN/FLARE/FS-RAG) and two stage RAG. The reranker of the two stage RAG is executed on GPU. pipelined through a streaming dataflow, facilitating finer￾grained computation-communication overlap than on GPUs; 3) the flexible memory system design maximizes HBM bandwidth u… view at source ↗
Figure 11
Figure 11. Figure 11: Left: End-to-end latency of the GPU-FPGA system vs.the baseline for memory as context method. Right: Latency for memory processing in memory as context. Similar to Titans, we use a linear projection on the current segment for query generation [PITH_FULL_IMAGE:figures/full_fig_p008_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: Left: End-to-end latency of the GPU-FPGA heteroge￾neous system vs. the GPU-centric system for MemAgent. Right: Latency for memory processing in MemAgent. 6.3. Energy Efficiency Another important aspect of LLM inference is energy ef￾ficiency, which directly affects serving cost [PITH_FULL_IMAGE:figures/full_fig_p008_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: Arithmetic intensity (FLOPs/byte) of memory processing pipeline and the rest operations in LLM inference for sparse attention, single-stage RAG, Memory as Context, and TTT/LaCT. For RAG, prepare memory is a one-time operation and will be amortized with multiple queries. minimize PCIe overhead. The standard method of communicating FPGA with GPU is through memory copy runtime APIs of each device and utilize… view at source ↗
Figure 14
Figure 14. Figure 14: Arithmetic intensity of memory rocessing pipeline and the rest operations in LLM inference for two-stage RAG. Each stage has a compute relevancy and retrieval step [PITH_FULL_IMAGE:figures/full_fig_p015_14.png] view at source ↗
Figure 15
Figure 15. Figure 15: (a) Standard cross device data transfer using memory copy for heterogeneous system. (b) PCIe P2P data transfer to bypass system DRAM accesses. • MemAgent: Transfers include KV cache and token IDs for each segment, taking approximately 14–218 ms. The corresponding GPU kernels take 17–534 s. These comparisons show that PCIe communication overhead remains small ( 1000x difference) relative to computation tim… view at source ↗
Figure 16
Figure 16. Figure 16: Transfer latency on PCIe bus against the transfer data size. For transferring indices (KB) and single-token KV embeddings (MB) are in the order of us, which is negligible compared to the latency of memory processing. between key vectors and all query heads, and weight-average them based on the query weights derived from the input token. The final scores are used for top-k selection for MLA module to atten… view at source ↗
Figure 17
Figure 17. Figure 17: FPGA kernel architecture for Memory as Context method. The kernel is a dataflow design with each module fully data driven compute a single operation. Past memory embeddings are cached in the HBM and the segment embeddings are loaded from CPU directly for each incoming segment. For MemAgent, the FPGA only perform the LLM decoding. Therefore, we can directly follow the designs in previous works (Zeng et al.… view at source ↗
Figure 18
Figure 18. Figure 18: FPGA kernel architecture for MemAgent. Following the design in prior works (Zeng et al., 2024; He et al., 2025c;b), we design the kernel specialized to LLM decoding, where the KV cache is delivered from the GPU through PCIe. Linear projection are executed in INT4 to align with the weight precision, and the rest operations (attention, SwiGLU, LayerNorm) are calculated at FP32 to maintain accuracy of the mo… view at source ↗
Figure 19
Figure 19. Figure 19: End-to-end latency of each sparse attention mechanism on the baseline and GPU-FPGA system with respect to the sequence length. H. Results with NVIDIA A100 Compared with the AMD MI210, the NVIDIA A100 is a more widely adopted GPU for LLM inference. Although we do not have access to a platform that hosts both the A100 and the U55C within the same node, we estimate the end-to-end latency by aggregating the m… view at source ↗
Figure 20
Figure 20. Figure 20: Latency of memory processing in each sparse attention mechanism with respect to the sequence length [PITH_FULL_IMAGE:figures/full_fig_p020_20.png] view at source ↗
Figure 21
Figure 21. Figure 21: End-to-end latency of each RAG system on the baseline system and GPU-FPGA system with respect to the document counts. 20 [PITH_FULL_IMAGE:figures/full_fig_p020_21.png] view at source ↗
Figure 22
Figure 22. Figure 22: Latency of memory processing in single stage RAG using BM25 as the retrieval heuristic (DRAGIN, FLARE, FS-RAG) and two stage RAG with respect to the document counts [PITH_FULL_IMAGE:figures/full_fig_p021_22.png] view at source ↗
Figure 23
Figure 23. Figure 23: Energy efficiency of sparse attention mechanisms in Joule per token. 21 [PITH_FULL_IMAGE:figures/full_fig_p021_23.png] view at source ↗
Figure 24
Figure 24. Figure 24: Energy efficiency of RAG systems in Joule per request [PITH_FULL_IMAGE:figures/full_fig_p022_24.png] view at source ↗
Figure 25
Figure 25. Figure 25: The relative speedup of end-to-end inference of DeepSeek V3.2 Exp with DeepSeek Attention when deployed on MI210, A100, MI210 + U55C, and A100 + U55C (estimated). A100 is generally faster in LLM inference than MI210. When integrating U55C with A100, the GPU-FPGA heterogeneous system can still speed up the inference. 22 [PITH_FULL_IMAGE:figures/full_fig_p022_25.png] view at source ↗
Figure 26
Figure 26. Figure 26: The relative speedup of memory processing in DeepSeek Attention when deployed on MI210, A100, MI210 + U55C, and A100 + U55C (estimated). Even with MI210, the GPU-FPGA heterogeneous system can still outperform A100. 23 [PITH_FULL_IMAGE:figures/full_fig_p023_26.png] view at source ↗

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