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Realization of graphene logics in an exciton-enhanced insulating phase

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arxiv 2110.02921 v1 pith:LS7BVA5L submitted 2021-10-06 cond-mat.mes-hall

Realization of graphene logics in an exciton-enhanced insulating phase

classification cond-mat.mes-hall
keywords graphenemathrminsulatingbilayerphasecarbondopingexcitonic
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved
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For two decades, two-dimensional carbon species, including graphene, have been the core of research in pursuing next-generation logic applications beyond the silicon technology. Yet the opening of a gap in a controllable range of doping, whilst keeping high conductance outside of this gapped state, has remained a grand challenge in them thus far. Here we show that, by bringing Bernal-stacked bilayer graphene in contact with an anti-ferromagnetic insulator CrOCl, a strong insulating behavior is observed in a wide range of positive total electron doping $n_\mathrm{tot}$ and effective displacement field $D_\mathrm{eff}$ at low temperatures. Transport measurements further prove that such an insulating phase can be well described by the picture of an inter-layer excitonic state in bilayer graphene owing to electron-hole interactions. The consequential over 1 $\mathrm{G\Omega}$ excitonic insulator can be readily killed by tuning $D_\mathrm{eff}$ and/or $n_\mathrm{tot}$, and the system recovers to a high mobility graphene with a sheet resistance of less than 100 $\mathrm{\Omega}$. It thus yields transistors with "ON-OFF" ratios reaching 10$^{7}$, and a CMOS-like graphene logic inverter is demonstrated. Our findings of the robust insulating phase in bilayer graphene may be a leap forward to fertilize the future carbon computing.

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