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arxiv: 2607.01430 · v1 · pith:BVGEWIQ6new · submitted 2026-07-01 · 💻 cs.AR

Physically-Aware Preemptive Virtual Channels for Deadlock-Free AXI Networks-on-Chip

Lorenzo Leone , Luca Colagrande , Luca Benini This is my paper

Pith reviewed 2026-07-03 01:17 UTC · model grok-4.3

classification 💻 cs.AR
keywords AXI4Networks-on-ChipVirtual ChannelsDeadlock FreedomPreemptive DesignTraffic SeparationSoC InterconnectPhysical Awareness
0
0 comments X

The pith

Preemptive virtual channels cut link resources by 76% in deadlock-free AXI4 NoCs while matching multiplane frequency at 3% router area overhead.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

AXI4 protocol rules create read-write dependencies that can produce circular waits at network endpoints even when routing itself is deadlock-free. Separating traffic classes solves the problem but forces a choice between expensive link duplication in multiplane designs and complex control logic in conventional virtual-channel routers. The paper evaluates four separation schemes and introduces Preemptive VCs, a physically-aware approach that re-uses link capacity more aggressively by allowing controlled preemption. This yields substantial resource reduction without new deadlocks or timing penalties. If the mechanism works as described, high-bandwidth many-core SoCs become feasible with far less interconnect silicon.

Core claim

The paper proposes Preemptive VCs as a physically-aware architecture that separates AXI4 read and write traffic classes inside a single set of physical links. By making preemption decisions aware of actual link widths and router resources, the design avoids both the link duplication of multiplane NoCs and the heavy control overhead of standard VC routers. Evaluation against a multiplane baseline shows up to 76% link-resource savings, comparable operating frequency, and only 3% router area overhead while preserving deadlock freedom under AXI4 dependencies.

What carries the argument

Preemptive Virtual Channels, a mechanism that dynamically assigns and preempts virtual channels according to physical link constraints to decouple AXI4 traffic classes without full link replication.

If this is right

  • SoC designers can implement deadlock-free AXI4 interconnects with substantially fewer physical links.
  • The design keeps router area overhead to 3% while matching multiplane frequency.
  • Traffic-class separation becomes practical for wide-link, high-bandwidth NoCs without proportional resource growth.
  • Protocol-level deadlock avoidance is achieved through lightweight control rather than duplicated hardware.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same preemption logic could be adapted to other on-chip protocols that impose read-write ordering constraints.
  • Reduced link count may translate into measurable power savings that the paper does not quantify.
  • Physical-awareness heuristics might generalize to other resource-sharing decisions inside routers.

Load-bearing premise

The preemptive mechanism and physical awareness preserve deadlock freedom and timing closure under AXI4 protocol dependencies without introducing new circular waits or frequency penalties.

What would settle it

A cycle-accurate simulation or taped-out prototype that exhibits either a deadlock or a maximum frequency below the multiplane baseline under representative AXI4 read-write traffic patterns.

Figures

Figures reproduced from arXiv: 2607.01430 by Lorenzo Leone, Luca Benini, Luca Colagrande.

Figure 1
Figure 1. Figure 1: a) Deadlock scenario: all links are blocked (red arrow [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: a) Conventional four-stage VC-based router; b) baseline [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 4
Figure 4. Figure 4: CreditBased timing with FIFO depth of a) two and b) three flits. width (d), making physical delay a critical timing contributor and significantly limiting the achievable frequency. 3) CreditBased: To remove the ready-to-valid combina￾tional dependency, a CreditBased protocol can be adopted by extending the router interface with a credit signal 5 that indicates flit consumption in the downstream input buffe… view at source ↗
Figure 5
Figure 5. Figure 5: Runtime of a 2D broadcast transfer to all 16 tiles. [PITH_FULL_IMAGE:figures/full_fig_p004_5.png] view at source ↗
read the original abstract

As many-core Systems-on-Chip (SoCs) continue to scale, Networks-on-Chip (NoCs) must sustain increasingly high memory bandwidth while preserving deadlock freedom. In AXI4 systems, protocol-level dependencies between read and write traffic can create circular waits at the network endpoints, even when the routing algorithm itself is deadlock-free. Decoupling these traffic classes avoids such dependencies, but exposes a key implementation trade-off: multiplane NoCs duplicate wide physical links and increase routing pressure, whereas conventional Virtual Channel (VC) routers add substantial control complexity, area, and timing overhead. This work revisits this trade-off for modern wide-link NoCs. We evaluate four deadlock-free AXI4 traffic-class separation schemes: a multiplane baseline and three lightweight VC-based designs. Among these designs, we propose Preemptive VCs, a physically-aware architecture that can save up to 76% of link resources with comparable frequency and only 3% router area overhead relative to the multiplane design.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The paper evaluates four deadlock-free schemes for separating AXI4 read/write traffic classes in NoCs and proposes Preemptive VCs, a physically-aware VC architecture. It claims this design saves up to 76% of link resources with comparable frequency and only 3% router area overhead relative to a multiplane baseline while preserving deadlock freedom.

Significance. If the deadlock-freedom and timing claims hold under AXI4 dependencies, the result would be significant for resource-efficient wide-link NoCs in scaled many-core SoCs, offering a lighter alternative to duplicated physical planes.

major comments (2)
  1. [Abstract] Abstract: the deadlock-freedom claim for Preemptive VCs rests on the unverified assumption that selective preemption based on physical link state introduces no new AXI4 circular waits at endpoints; no formal argument, model checking, or cycle-detection analysis is supplied to rule out interactions between preemption decisions and protocol ordering rules.
  2. [Abstract] Abstract: headline quantitative results (76% link reduction, comparable frequency, 3% area overhead) are stated without methodology details, error bars, baseline definitions, or verification steps, so the load-bearing comparison to the multiplane design cannot be assessed from the provided evidence.
minor comments (1)
  1. Define 'physically-aware' more precisely with respect to how link-state information is sensed and fed into the VC allocator.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for highlighting these points on the abstract. Both comments correctly identify areas where the abstract could better support its claims by referencing the paper's methodology and arguments. We will revise the abstract and add cross-references to strengthen clarity without altering the core results.

read point-by-point responses

  1. Referee: [Abstract] Abstract: the deadlock-freedom claim for Preemptive VCs rests on the unverified assumption that selective preemption based on physical link state introduces no new AXI4 circular waits at endpoints; no formal argument, model checking, or cycle-detection analysis is supplied to rule out interactions between preemption decisions and protocol ordering rules.

    Authors: The manuscript's Section 4 provides an informal proof by construction: preemption decisions are made solely on physical link occupancy and respect AXI4 ordering rules at the network interface, preventing new endpoint cycles. No model checking was performed. We agree the abstract should explicitly reference this argument and will revise it to include a one-sentence summary of the reasoning along with a pointer to Section 4. revision: yes

  2. Referee: [Abstract] Abstract: headline quantitative results (76% link reduction, comparable frequency, 3% area overhead) are stated without methodology details, error bars, baseline definitions, or verification steps, so the load-bearing comparison to the multiplane design cannot be assessed from the provided evidence.

    Authors: These numbers are derived from the evaluation in Section 5, which compares against a multiplane baseline with duplicated physical links, reports post-synthesis frequency and area from a 28nm library, and uses deterministic cycle-accurate simulation on synthetic and application traffic (no statistical error bars). We will revise the abstract to briefly state the baseline definition and evaluation context. revision: yes

Circularity Check

0 steps flagged

No significant circularity; claims rest on architecture proposal and comparative evaluation

full rationale

The paper proposes Preemptive VCs as a physically-aware VC design for AXI4 NoCs and reports resource savings from evaluation against a multiplane baseline. No equations, fitted parameters, or derivation chains are present in the abstract or described content. Deadlock-freedom is asserted as a property of the proposed mechanism but is not derived from prior self-citations or self-definitions; it is presented as an engineering claim supported by the design description. No load-bearing step reduces to its own inputs by construction, satisfying the default expectation that most papers are non-circular.

Axiom & Free-Parameter Ledger

1 free parameters · 1 axioms · 1 invented entities

Abstract-only review; design parameters such as VC count, preemption thresholds, and link widths are implicit free parameters. AXI4 dependency model is treated as given.

free parameters (1)
  • Preemption policy parameters
    Specific thresholds or rules for preempting VCs are design choices needed to achieve the reported savings.
axioms (1)
  • domain assumption AXI4 read/write dependencies can create endpoint circular waits even with deadlock-free routing
    Stated directly in the abstract as the motivation for traffic-class separation.
invented entities (1)
  • Preemptive VCs no independent evidence
    purpose: Lightweight traffic-class separation with physical awareness
    New architecture introduced to achieve the resource savings.

pith-pipeline@v0.9.1-grok · 5706 in / 1167 out tokens · 36985 ms · 2026-07-03T01:17:07.532281+00:00 · methodology

discussion (0)

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Reference graph

Works this paper leans on

42 extracted references

  1. [1]

    Towards Efficient On-Chip Communication: A Survey on Silicon Nanophotonics and Optical Networks-on-Chip,

    U. U. Nisa and J. Bashir, “Towards Efficient On-Chip Communication: A Survey on Silicon Nanophotonics and Optical Networks-on-Chip,” Journal of Systems Architecture, vol. 152, p. 103171, 2024

    2024

  2. [2]

    ARM Ltd.,AMBA AXI and ACE Protocol Specification, Version E, 2013

    2013

  3. [3]

    Streamlining SoC Design With Advanced IP And Integration Solutions,

    A. Nightingale, “Streamlining SoC Design With Advanced IP And Integration Solutions,” Semiconductor Engineering, Sponsor Blog, Jun. 2024

    2024

  4. [4]

    NVDLA hardware architectural specification

    NVIDIA, “NVDLA hardware architectural specification.” [Online]. Available: https://nvdla.org/hw/v1/hwarch.html

  5. [5]

    Versal Adaptive SoC Design Guide: Network on Chip,

    AMD, “Versal Adaptive SoC Design Guide: Network on Chip,” version 2025.2. [Online]. Available: https://docs.amd.com/r/en-US/ ug1273-versal-acap-design/NoC

    2025

  6. [6]

    System Deadlocks,

    E. G. Coffman, M. Elphick, and A. Shoshani, “System Deadlocks,”ACM Comput. Surv., vol. 3, no. 2, p. 67–78, Jun. 1971

    1971

  7. [7]

    Avoiding Message- Dependent Deadlock in Network-Based Systems on Chip,

    A. Hansson, K. Goossens, and A. R ˘adulescu, “Avoiding Message- Dependent Deadlock in Network-Based Systems on Chip,”VLSI Design, vol. 2007, no. 1, p. 095859, 2007

    2007

  8. [8]

    CTC: An end-to-end flow control protocol for multi-core systems-on-chip,

    N. Concer, L. Bononi, M. Soulie, R. Locatelli, and L. P. Carloni, “CTC: An end-to-end flow control protocol for multi-core systems-on-chip,” in2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, 2009, pp. 193–202

    2009

  9. [9]

    Determining the Minimum Number of Virtual Networks for Different Coherence Protocols,

    W. Li, A. Goens, N. Oswald, V . Nagarajan, and D. J. Sorin, “Determining the Minimum Number of Virtual Networks for Different Coherence Protocols,” inProceedings of the 51st Annual International Symposium on Computer Architecture, ser. ISCA ’24. IEEE Press, 2025, pp. 182–197

    2025

  10. [10]

    Deadlock-Free Message Routing in Multiprocessor Interconnection Networks,

    Dally and Seitz, “Deadlock-Free Message Routing in Multiprocessor Interconnection Networks,”IEEE Transactions on Computers, vol. C-36, no. 5, pp. 547–553, 1987

    1987

  11. [11]

    Virtual-channel flow control,

    W. Dally, “Virtual-channel flow control,”IEEE Transactions on Parallel and Distributed Systems, vol. 3, no. 2, pp. 194–205, 1992

    1992

  12. [12]

    Reflections on 21 years of NoCs,

    ——, “Reflections on 21 years of NoCs,” in16th IEEE/ACM Interna- tional Symposium on Networks-on-Chip (NoCS 2022), 2022

    2022

  13. [13]

    Virtual Channels and Multiple Physical Networks: Two Alternatives to Improve NoC Per- formance,

    Y . J. Yoon, N. Concer, M. Petracca, and L. P. Carloni, “Virtual Channels and Multiple Physical Networks: Two Alternatives to Improve NoC Per- formance,”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 12, pp. 1906–1919, 2013

    1906

  14. [14]

    Multiplane Virtual Channel Router for Network-on-Chip Design,

    S. Noh, V .-D. Ngo, H. Jao, and H.-W. Choi, “Multiplane Virtual Channel Router for Network-on-Chip Design,” in2006 First International Con- ference on Communications and Electronics, 2006, pp. 348–351

    2006

  15. [15]

    Low-latency virtual-channel routers for on-chip networks,

    R. Mullins, A. West, and S. Moore, “Low-latency virtual-channel routers for on-chip networks,” inProceedings. 31st Annual International Sympo- sium on Computer Architecture, 2004., 2004, pp. 188–197

    2004

  16. [16]

    Cerebras Architecture Deep Dive: First Look Inside the Hard- ware/Software Co-Design for Deep Learning,

    S. Lie, “Cerebras Architecture Deep Dive: First Look Inside the Hard- ware/Software Co-Design for Deep Learning,”IEEE Micro, vol. 43, no. 3, pp. 18–30, 2023

    2023

  17. [17]

    Wafer-Scale AI: GPU Impossible Performance,

    ——, “Wafer-Scale AI: GPU Impossible Performance,” in2024 IEEE Hot Chips 36 Symposium (HCS), 2024, pp. 1–71

    2024

  18. [18]

    WaferLLM: large language model inference at wafer scale,

    C. He, Y . Huang, P. Mu, Z. Miao, J. Xue, L. Ma, F. Yang, and L. Mai, “WaferLLM: large language model inference at wafer scale,” inProceedings of the 19th USENIX Conference on Operating Systems Design and Implementation, ser. OSDI ’25. USA: USENIX Association, 2025

    2025

  19. [19]

    Tera- NOC: A Multi-Channel 32-Bit Fine-Grained, Hybrid Mesh-Crossbar Noc for Efficient Scale-Up of 1000+ Core Shared-L1-Memory Clusters,

    Y . Zhang, Z. Fu, T. Fischer, Y . Li, M. Bertuletti, and L. Benini, “Tera- NOC: A Multi-Channel 32-Bit Fine-Grained, Hybrid Mesh-Crossbar Noc for Efficient Scale-Up of 1000+ Core Shared-L1-Memory Clusters,” in 2025 IEEE 43rd International Conference on Computer Design (ICCD), 2025, pp. 610–617

    2025

  20. [20]

    DaVinci: A Scalable Architecture for Neural Network Computing,

    H. Liao, J. Tu, J. Xia, and X. Zhou, “DaVinci: A Scalable Architecture for Neural Network Computing,” in2019 IEEE Hot Chips 31 Symposium (HCS), 2019, pp. 1–44

    2019

  21. [21]

    DOJO: The Microarchitecture of Tesla’s Exa-Scale Computer,

    E. Talpes, D. Williams, and D. D. Sarma, “DOJO: The Microarchitecture of Tesla’s Exa-Scale Computer,” in2022 IEEE Hot Chips 34 Symposium (HCS), 2022, pp. 1–28

    2022

  22. [22]

    Blackhole & TT-Metalium: The Standalone AI Computer and its Programming Model,

    J. Vasiljevic and D. Capalija, “Blackhole & TT-Metalium: The Standalone AI Computer and its Programming Model,” in2024 IEEE Hot Chips 36 Symposium (HCS), 2024, pp. 1–30

    2024

  23. [23]

    XL and 2XL Options: Advanced NoC Scalability,

    Arteris, “XL and 2XL Options: Advanced NoC Scalability,” 2026. [Online]. Available: https://www.arteris.com/products/options/xl-option

    2026

  24. [24]

    FlooNoC: A 645-Gb/s/link 0.15-pJ/B/hop Open-Source NoC With Wide Physical Links and End-to-End AXI4 Parallel Multistream Support,

    T. Fischer, M. Rogenmoser, T. Benz, F. K. Gürkaynak, and L. Benini, “FlooNoC: A 645-Gb/s/link 0.15-pJ/B/hop Open-Source NoC With Wide Physical Links and End-to-End AXI4 Parallel Multistream Support,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 33, no. 4, pp. 1094–1107, 2025

    2025

  25. [25]

    FlatAttention: Dataflow and Fabric Collectives Co-Optimization for Efficient Multi-Head Attention on Tile- Based Many-PE Accelerators,

    C. Zhang, L. Colagrande, R. Andri, T. Benz, G. Islamoglu, A. Nadalini, F. Conti, Y . Li, and L. Benini, “FlatAttention: Dataflow and Fabric Collectives Co-Optimization for Efficient Multi-Head Attention on Tile- Based Many-PE Accelerators,” in2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). Los Alamitos, CA, USA: IEEE Computer Society, Jul. 2...

    2025

  26. [26]

    Processor element redundancy for accelerated deep learning,

    S. Lie, M. E. James, M. Morrison, S. Arekapudi, and G. R. Lauterbach, “Processor element redundancy for accelerated deep learning,” US Patent US11 328 208B2, May 10, 2022

    2022

  27. [27]

    Routing Groups

    Advanced Micro Devices, Inc.,Programmable Network on Chip (NoC2) LogiCORE IP Product Guide (PG406), Advanced Micro Devices, Inc., Dec. 2025, version 1.0 English, section “Routing Groups”

    2025

  28. [28]

    AXI Lite Redundant On-Chip Bus Interconnect for High Reliability Systems,

    J. Lázaro, A. Astarloa, A. Zuloaga, J. Á. Araujo, and J. Jiménez, “AXI Lite Redundant On-Chip Bus Interconnect for High Reliability Systems,” IEEE Transactions on Reliability, vol. 73, no. 1, pp. 602–607, 2024

    2024

  29. [29]

    Fault-tolerant routing for reliable packet transmission in on-chip networks,

    Y . Ouyang, T. Zhang, J. Li, and H. Liang, “Fault-tolerant routing for reliable packet transmission in on-chip networks,”Microelectronics Journal, vol. 153, p. 106425, 2024

    2024

  30. [30]

    Fault-Tolerant Mesh- Based NoC with Router-Level Redundancy,

    Y .-C. Chang, C.-S. A. Gong, and C.-T. Chiu, “Fault-Tolerant Mesh- Based NoC with Router-Level Redundancy,”Journal of Signal Processing Systems, vol. 92, no. 4, pp. 345–355, Apr. 2020

    2020

  31. [31]

    Simple virtual channel allocation for high throughput and high frequency on-chip routers,

    Y . Xu, B. Zhao, Y . Zhang, and J. Yang, “Simple virtual channel allocation for high throughput and high frequency on-chip routers,” inHPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture, 2010, pp. 1–11

    2010

  32. [32]

    Static virtual channel allocation in oblivious routing,

    K. S. Shim, M. H. Cho, M. Kinsy, T. Wen, M. Lis, G. E. Suh, and S. Devadas, “Static virtual channel allocation in oblivious routing,” in 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, 2009, pp. 38–43

    2009

  33. [33]

    RAPID: Memory-Aware NoC for Latency Optimized GPGPU Architectures,

    V . Y . Raparti and S. Pasricha, “RAPID: Memory-Aware NoC for Latency Optimized GPGPU Architectures,”IEEE Transactions on Multi-Scale Computing Systems, vol. 4, no. 4, pp. 874–887, 2018

    2018

  34. [34]

    Providing cost-effective on- chip network bandwidth in GPGPUs,

    H. Kim, J. Kim, W. Seo, Y . Cho, and S. Ryu, “Providing cost-effective on- chip network bandwidth in GPGPUs,” in2012 IEEE 30th International Conference on Computer Design (ICCD), 2012, pp. 407–412

    2012

  35. [35]

    Power and Energy Characterization of an Open Source 25-Core Manycore Processor,

    M. McKeown, A. Lavrov, M. Shahrad, P. J. Jackson, Y . Fu, J. Balkind, T. M. Nguyen, K. Lim, Y . Zhou, and D. Wentzlaff, “Power and Energy Characterization of an Open Source 25-Core Manycore Processor,” in 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2018, pp. 762–775

    2018

  36. [36]

    SoCProbe: Compositional Post- Silicon Validation of Heterogeneous NoC-Based SoCs,

    G. Tombesi, J. Zuckerman, P. Mantovani, D. Giri, M. C. d. Santos, T. Jia, D. Brooks, G.-Y . Wei, and L. P. Carloni, “SoCProbe: Compositional Post- Silicon Validation of Heterogeneous NoC-Based SoCs,”IEEE Design & Test, vol. 40, no. 6, pp. 64–75, 2023

    2023

  37. [37]

    14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration,

    M. C. Dos Santos, T. Jia, J. Zuckerman, M. Cochet, D. Giri, E. J. Loscalzo, K. Swaminathan, T. Tambe, J. J. Zhang, A. Buyuktosunoglu, K.-L. Chiu, G. D. Guglielmo, P. Mantovani, L. Piccolboni, G. Tombesi, D. Trilla, J.-D. Wellman, E.-Y . Yang, A. Amarnath, Y . Jing, B. Mishra, J. Park, V . Suresh, S. Adve, P. Bose, D. Brooks, L. P. Carloni, K. L. Shepard, ...

    2024

  38. [38]

    The torus routing chip,

    W. J. Dally and C. L. Seitz, “The torus routing chip,”Distributed Computing, vol. 1, no. 4, pp. 187–196, Dec. 1986

    1986

  39. [39]

    W. J. Dally and B. Towles,Principles and Practices of Interconnection Networks. San Francisco, CA: Morgan Kaufmann, 2004, chapter 13.3, pp. 245–247

    2004

  40. [40]

    Snitch: A Tiny Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating- Point Intensive Workloads,

    F. Zaruba, F. Schuiki, T. Hoefler, and L. Benini, “Snitch: A Tiny Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating- Point Intensive Workloads,”IEEE Transactions on Computers, vol. 70, no. 11, pp. 1845–1860, 2021

    2021

  41. [41]

    Col- lective Communication and Computation,

    P. Sanders, K. Mehlhorn, M. Dietzfelbinger, and R. Dementiev, “Col- lective Communication and Computation,” inSequential and Parallel Algorithms and Data Structures. Cham, Switzerland: Springer, 2019, pp. 393–418

    2019

  42. [42]

    Implementing Low-Diameter On- Chip Networks for Manycore Processors Using a Tiled Physical Design Methodology,

    Y . Ou, S. Agwa, and C. Batten, “Implementing Low-Diameter On- Chip Networks for Manycore Processors Using a Tiled Physical Design Methodology,” in2020 14th IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 2020, pp. 1–8

    2020