Llm-aided efficient hardware design automation

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• OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design cs.CL · 2026-06-09 · unverdicted · none · ref 11

  OpenRTLSet supplies 131k+ Verilog samples with AI-generated descriptions to enable fine-tuning of LLMs for hardware module design.

• TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog cs.AR · 2026-04-26 · conditional · none · ref 7

  TimingLLM uses a fine-tuned LLM to generate structural timing cues from Verilog followed by a retrieval-augmented regressor with a learned steering vector to predict WNS and TNS with R values of 0.91 and 0.97.

• VeriPilot: An LLM-Powered Verilog Debugging Framework cs.AR · 2026-06-22 · unverdicted · none · ref 27

  VeriPilot raises GPT-4o Verilog repair success from 54.3% to 85.71% on the CVDP benchmark by using golden-model semantic alignment and CDFG-based signal tracing.

• Foundational Design Principles and Patterns for Building Robust and Adaptive GenAI-Native Systems cs.SE · 2025-08-21 · unverdicted · none · ref 64

  Proposes five foundational pillars and architectural patterns for building robust GenAI-native systems by combining AI with software engineering principles.

• Surveying GenAI-based Automation in Printed Circuit Board Design and Test cs.AR · 2026-06-10 · unverdicted · none · ref 111

  Survey of GenAI in PCB design lifecycle presenting taxonomy, technical challenges, and research directions.